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Out-of-order execution
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#	Item
11	The Alpha[removed]Microprocessor: Out-of-Order Execution at 600 Mhz R. E. Kessler COMPAQ Computer Corporation Shrewsbury, MA Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:48:29 Central processing unit CPU cache Cache Computer memory Instruction set architectures Alpha 21264 Branch predictor Out-of-order execution DEC Alpha Computer architecture Computer hardware Computer engineering
12	PDF Document Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:43:57 Central processing unit Classes of computers Parallel computing Superscalar Instruction set architectures Out-of-order execution Instruction-level parallelism Branch predictor CPU cache Computer architecture Computer hardware Computing
13	COMPUTING THE WORST CASE EXECUTION TIME OF AN AVIONICS PROGRAM BY ABSTRACT INTERPRETATION Jean Souyris* ([removed]), Erwan Le Pavec* ([removed]), Guillaume Himbert* (guillaume.himbert@airbus. Add to Reading List Source URL: www.absint.com Language: English - Date: 2011-01-26 09:33:00 Technology Worst-case execution time CPU cache Parallel computing Computer Central processing unit Pointer Out-of-order execution Real-time computing Computing Electronics
14	Speculative Updates of Local and Global Branch History: A Quantitative Analysis Kevin Skadron SKADRON @ CS . VIRGINIA . EDU Add to Reading List Source URL: www.jilp.org Language: English - Date: 2003-06-05 15:33:55 Central processing unit Instruction set architectures Branch predictor Alpha 21264 CPU cache Out-of-order execution Register renaming Microarchitecture DEC Alpha Computer architecture Computer engineering Computer hardware
15	DYNAMIC FREQUENCY AND VOLTAGE SCALING FOR A MULTIPLE-CLOCK-DOMAIN MICROPROCESSOR MULTIPLE CLOCK DOMAINS IS ONE SOLUTION TO THE INCREASING PROBLEM OF PROPAGATING THE CLOCK SIGNAL ACROSS INCREASINGLY LARGER AND Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2004-01-21 17:37:54 Central processing unit Parallel computing Microprocessors Energy conservation Alpha 21264 Dynamic voltage scaling Frequency scaling Multi-core processor Out-of-order execution Computer hardware Computer architecture Computing
16	--06 April 20, 2000 Cheap Out-of-Order Execution using Delayed Issue J.P. Grossman Add to Reading List Source URL: www.ai.mit.edu Language: English - Date: 2001-05-16 17:41:22 Parallel computing Central processing unit Classes of computers Register renaming Superscalar Very long instruction word Software pipelining Tomasulo algorithm Instruction set Computer architecture Computing Computer engineering
17	Appeared in the Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October[removed]Performance of Database Workloads on Shared-Memory Systems with Out-of-Order Processors Parthas Add to Reading List Source URL: barroso.org Language: English - Date: 2005-03-07 23:35:18 Computer engineering Cache CPU cache Computer memory Microarchitecture Out-of-order execution Instruction-level parallelism Pentium Pro Parallel computing Computer architecture Computer hardware Central processing unit
18	Print Order Routing In arranging for the execution of equities and listed options orders, Schwab seeks out industry-leading execution services and access to the best-performing markets. Schwab routes equity and options Add to Reading List Source URL: forefrontgroup.com Language: English - Date: 2014-05-12 12:39:58 Economy of the United States Stock market Order NYSE Arca Market maker NASDAQ Chicago Board Options Exchange New York Stock Exchange Boston Options Exchange Financial economics Financial markets Investment
19	Design and Evaluation of a RISC Processor with a Tomasulo Scheduler Diplomarbeit Lehrstuhl f¨ur Rechnerarchitektur Add to Reading List Source URL: www.kroening.com Language: English - Date: 2014-05-11 10:55:21 Classes of computers Algorithms Tomasulo algorithm DLX Out-of-order execution Central processing unit Reduced instruction set computing MIPS architecture Instruction pipeline Computer architecture Computing Instruction set architectures
20	In-order vs. Out-of-order Execution In-order instruction execution • instructions are fetched, executed & completed in compilergenerated order Add to Reading List Source URL: courses.cs.washington.edu Language: English - Date: 2006-10-19 17:44:22 Central processing unit Out-of-order execution Hazard Speculative execution Instruction set Memory disambiguation Classic RISC pipeline Computer architecture Computer hardware Computer engineering

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